Internal Interrupts; Interrupt Exception Handling Vector Table; Figure 5.3 Block Diagram Of Interrupts Kin9 To Kin0 And Wue15 To Wue8 - Renesas H8S/2158 User Manual

Section 5 Interrupt Controller
KMIMn
KINn input
Note: n = 9 to 0

Figure 5.3 Block Diagram of Interrupts KIN9 to KIN0 and WUE15 to WUE8

5.4.2

Internal Interrupts

Internal interrupts issued from the on-chip peripheral modules have the following features:
• For each on-chip peripheral module there are flags that indicate the interrupt request status,
and enable bits that individually select enabling or disabling of these interrupts. When the
enable bit for a particular interrupt source is set to 1, an interrupt request is sent to the interrupt
controller.
• The control level for each interrupt can be set by ICR.
• The DTC can be activated by an interrupt request from an on-chip peripheral module.
• An interrupt request that activates the DTC is not affected by the interrupt control mode or the
status of the CPU interrupt mask bits.
5.5

Interrupt Exception Handling Vector Table

Table 5.3 lists interrupt exception handling sources, vector addresses, and interrupt priorities. For
default priorities, the lower the vector number, the higher the priority. Modules set at the same
priority will conform to their default priorities. Priorities within a module are fixed.
An interrupt control level can be specified for a module to which an ICR bit is assigned. Interrupt
requests from modules that are set to interrupt control level 1 (priority) by the ICR bit setting and
the I and UI bits in CCR are given priority and processed before interrupt requests from modules
that are set to interrupt control level 0 (no priority).
Rev. 3.00 Jan 25, 2006 page 86 of 872
REJ09B0286-0300
Falling-edge
detection circuit
Clear signal
(Example of KIN9 to KIN0)
KINn interrupt request
S Q
R