Interrupt; External Interrupts; Figure 5.2 Block Diagram Of Interrupts Irq0 To Irq5 - Renesas H8S Series Hardware Manual

5.4

Interrupt

5.4.1

External Interrupts

There are seven external interrupts: NMI and IRQ0 to IRQ5. These interrupts can be used to
restore this LSI from software standby mode.
NMI Interrupt: NMI is the highest-priority interrupt, and is always accepted by the CPU
regardless of the interrupt control mode or the status of the CPU interrupt mask bits. The NMIEG
bit in SYSCR can be used to select whether an interrupt is requested at a rising edge or a falling
edge on the NMI pin.
IRQ0 to IRQ5 Interrupts: Interrupts IRQ0 to IRQ5 are requested by an input signal at pins IRQ0
to IRQ5. Interrupts IRQ0 to IRQ5 have the following features:
• Using ISCR, it is possible to select whether an interrupt is generated by a low level, falling
edge, rising edge, or both edges, at pins IRQ0 to IRQ5.
• Enabling or disabling of interrupt requests IRQ0 to IRQ5 can be selected with IER.
• The interrupt priority level can be set with IPR.
• The status of interrupt requests IRQ0 to IRQ5 is indicated in ISR. ISR flags can be cleared to 0
by software.
The detection of IRQ0 to IRQ5 interrupts does not depend on whether the relevant pin has been
set for input or output. However, when a pin is used as an external interrupt input pin, do not clear
the corresponding DDR to 0; and use the pin as an I/O pin for another function.
A block diagram of interrupts IRQ0 to IRQ5 is shown in figure 5.2.
IRQn input
Note: n = 5 to 0

Figure 5.2 Block Diagram of Interrupts IRQ0 to IRQ5

IRQnSCA, IRQnSCB
Edge/level
detection circuit
Clear signal
Section 5 Interrupt Controller
IRQnE
IRQnF
S Q
R
Rev. 6.00 Mar 15, 2006 page 75 of 570
IRQn interrupt
request
REJ09B0211-0600