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Section 7 DMA Controller
7.1.4
Input/Output Pins
Table 7.2 lists the DMAC pins.
Table 7.2
DMAC Pins
Channel
Name
0
DMA request 0
Transfer end 0
1
DMA request 1
Transfer end 1
Note: External requests cannot be made to channel A in short address mode.
7.1.5
Register Configuration
Table 7.3 lists the DMAC registers.
Rev. 4.00 Jan 26, 2006 page 212 of 938
REJ09B0276-0400
Abbrevia-
Input/
tion
Output
DREQ
Input
0
TEND
Output
0
DREQ
Input
1
TEND
Output
1
Function
External request for DMAC channel 0
Transfer end on DMAC channel 0
External request for DMAC channel 1
Transfer end on DMAC channel 1
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