Input/Output Pins; Register Descriptions - Renesas H8S Series Hardware Manual

5.2

Input/Output Pins

Table 5.1 summarizes the pins of the interrupt controller.
Table 5.1 Pin Configuration
Name
NMI
IRQ5
IRQ4
IRQ3
IRQ2
IRQ1
IRQ0
5.3

Register Descriptions

The interrupt controller has the following registers. For details on system control register
(SYSCR), refer to section 3.2.2, System Control Register (SYSCR). For details on register
addresses and register states during each process, refer to appendix A, On-Chip I/O Register.
• System control register (SYSCR)
• IRQ sense control register H (ISCRH)
• IRQ sense control register L (ISCRL)
• IRQ enable register (IER)
• IRQ status register (ISR)
• Interrupt priority register A (IPRA)
• Interrupt priority register B (IPRB)
• Interrupt priority register C (IPRC)
• Interrupt priority register D (IPRD)
• Interrupt priority register E (IPRE)
• Interrupt priority register F (IPRF)
• Interrupt priority register G (IPRG)
• Interrupt priority register H (IPRH)
• Interrupt priority register J (IPRJ)
• Interrupt priority register K (IPRK)
• Interrupt priority register M (IPRM)
I/O Function
Input Nonmaskable external interrupt
Rising or falling edge can be selected
Input Maskable external interrupts
Input
Rising, falling, or both edges, or level sensing, can be selected
Input
Input
Input
Input
Section 5 Interrupt Controller
Rev. 6.00 Mar 15, 2006 page 69 of 570
REJ09B0211-0600