Interrupt Controller; Features - Renesas RZ/A Series User Manual

RZ/A1L Group, RZ/A1LU Group, RZ/A1LC Group
7.

Interrupt Controller

The interrupt controller ascertains the priority of interrupt sources and controls interrupt requests to the CPU. The
interrupt controller registers set the order of priority of each interrupt, allowing the user to process interrupt requests
according to the user-set priority.
7.1

Features

• 32 levels of interrupt priority can be set.
By setting the interrupt priority registers, the priorities of IRQ interrupts, on-chip peripheral module interrupts, and
pin interrupts can be selected from 32 levels for request sources.
• NMI noise canceler function
An NMI input-level bit indicates the NMI pin state. By reading this bit in the interrupt exception service routine, the
pin state can be checked, enabling it to be used as the noise canceler function.
®
• Arm PrimeCell
generic interrupt controller (PL390)*
Note: * The PL390 supports version 1 of the specification for the architecture of the Arm generic interrupt controller
(GIC).
R01UH0437EJ0600 Rev.6.00
Jan 29, 2021
7. Interrupt Controller
7-1