Section 5 Interrupt Controller; Overview; Features - Renesas H8/3067 Series User Manual

5.1

Overview

5.1.1

Features

The interrupt controller has the following features:
• Interrupt priority registers (IPRs) for setting interrupt priorities
Interrupts other than NMI can be assigned to two priority levels on a module-by-module basis
in interrupt priority registers A and B (IPRA and IPRB).
• Three-level masking by the I and UI bits in the CPU condition code register (CCR)
• Seven external interrupt pins
NMI has the highest priority and is always accepted*; either the rising or falling edge can be
selected. For each of IRQ
independently.
Note: * In the flash memory and flash memory R versions, NMI input is sometimes disabled. For
details see 18.6.4, NMI Input Disable Conditions.

Section 5 Interrupt Controller

to IRQ , sensing of the falling edge or level sensing can be selected
0 5
Section 5 Interrupt Controller
Rev. 4.00 Jan 26, 2006 page 91 of 938
REJ09B0276-0400