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Section 11 8-Bit Timer (TMR)
11.6.3
Conflict between TCOR Write and Compare-Match
If a compare-match occurs during the T
TCOR write takes priority and the compare-match signal is disabled.
φ
Address
Internal write signal
TCNT
TCOR
Compare-match signal
Figure 11.9 Conflict between TCOR Write and Compare-Match
Rev. 1.00 Mar. 12, 2008 Page 410 of 1178
REJ09B0403-0100
state of a TCOR write cycle as shown in figure 11.9, the
2
TCOR write cycle by CPU
T 1
T 2
TCOR address
N
N
N + 1
M
TCOR write data
Disabled
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