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Section 8 I/O Ports
• PD4/CLKRUN
The pin function is switched as shown below according to the PD4DDR bit. This pin can be
used as the CLKRUN input pin when the LPC is enabled.
LPC
PD4DDR
Pin function
• PD3/GA20
The pin function is switched as shown below according to the combination of the FGA20E bit
in HICR0 of the LPC and the PD3DDR bit.
FGA20E
PD3DDR
Pin function
• PD2/PME
The pin function is switched as shown below according to the combination of the PMEE bit in
HICR0 of the LPC and the PD2DDR bit.
PMEE
PD2DDR
Pin function
• PD1/LSMI
The pin function is switched as shown below according to the combination of the LSMIE bit in
HICR0 of the LPC and the PD1DDR bit.
LSMIE
PD1DDR
Pin function
Rev. 1.00 Mar. 12, 2008 Page 260 of 1178
REJ09B0403-0100
Disabled
0
PD4 input pin
0
0
PD3 input pin
0
0
PD2 input pin
0
0
PD1 input pin
1
PD4 output pin
1
PD3 output pin
1
PD2 output pin
1
PD1 output pin
Enabled
0
CLKRUN input/output pin
1
0
GA20 output pin
1
0
PME output pin
1
0
LSMI output pin
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