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Bit
Bit Name
3
RSME
2
1
ASCE
0
—
Initial
Value
R/W
Description
R/W
Resume Enable
0
This bit releases the suspend state (or executes
remote wakeup). When RSME is set to 1, resume
request starts. If RSME is once set to 1, clear this bit
to 0 again afterwards. In this case, the value 1 set to
RSME must be kept for at least one clock period of
12-MHz clock.
Reserved
0
R
This bit is always read as 0. The initial value should
not be changed.
R/W
Automatic Stall Clear Enable
0
Setting the ASCE bit to 1 automatically clears the stall
setting bit (the EPxSTL (x = 1, 2, or 3) bit in EPSTLR0
or EPSTR1) of the end point that has returned the
stall handshake to the host. The automatic stall clear
enable is common to the all end points. Thus the
individual control of the end point is not possible.
When the ASCE bit is set to 0, the stall setting bit is
not automatically cleared. This bit must be released
by the users. To enable this bit, make sure that the
ASCE bit should be set to 1 before the EPxSTL (x = 1,
2, or 3) bit in EPSTL is set to 1.
Reserved
0
R
This bit is always read as 0. The initial value should
not be changed.
Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 855 of 1178
REJ09B0403-0100
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