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6.5
Bus Interface
The normal extended bus interface enables direct connection to ROM and SRAM. For details on
selection of the bus specifications for the basic extended area and 256-Kbyte extended area, see
table 6.5.
The address-data multiplex extended bus interface enables direct connection to products that
supports this bus interface. For details on selection of the bus specifications for the IOS extended
area and 256-Kbyte extended area, see tables 6.8 to 6.11.
6.5.1
Data Size and Data Alignment
Data sizes for the CPU and other internal bus masters are byte, word, and longword. The BSC has
a data alignment function, and controls whether the upper data bus (D15 to D8/AD15 to AD8) or
lower data bus (D7 to D0/AD7 to AD0) is used when the external address space is accessed,
according to the bus specifications for the area being accessed (8-bit access space or 16-bit access
space) and the data size.
(1)
8-Bit Access Space
Figure 6.3 illustrates data alignment control for the 8-bit access space. With the 8-bit access space,
the upper data bus (D15 to D8) is always used for accesses. The amount of data that can be
accessed at one time is one byte: a word access is performed as two byte accesses, and a longword
access, as four byte accesses.
The lower data bus (AD7 to AD0) is used in address-data multiplex extended mode.
Byte size
Word size
Longword
size
Figure 6.3 Access Sizes and Data Alignment Control (8-bit Access Space)
D15
7
15
1st bus cycle
7
2nd bus cycle
31
1st bus cycle
23
2nd bus cycle
15
3rd bus cycle
7
4th bus cycle
Section 6 Bus Controller (BSC)
Upper data bus
Lower data bus
D8 D7
0
8
0
24
16
8
0
Rev. 1.00 Mar. 12, 2008 Page 125 of 1178
D0
REJ09B0403-0100
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