13.8 Interrupt Sources................................................................................................................ 487
13.8.1 Interrupts in Normal Serial Communication Interface Mode ............................... 487
13.9 Usage Notes ....................................................................................................................... 489
13.9.1 Module Stop Mode Setting ................................................................................... 489
13.9.2 Break Detection and Processing ........................................................................... 489
13.9.3 Mark State and Break Sending.............................................................................. 489
13.9.4 Receive Error Flags and Transmit Operations
(Clock Synchronous Mode Only) ......................................................................... 489
13.9.5 Relation between Writing to TDR and TDRE Flag .............................................. 489
14.1 Features.............................................................................................................................. 497
14.2 Register Descriptions ......................................................................................................... 498
14.2.1 CRC Control Register (CRCCR) .......................................................................... 498
14.2.3 CRC Data Output Register (CRCDOR)................................................................ 499
14.3 CRC Operation Circuit Operation...................................................................................... 499
15.1 Features.............................................................................................................................. 505
15.2 Input/Output Pins ............................................................................................................... 507
15.3 Register Descriptions ......................................................................................................... 508
15.3.2 Receive Buffer Register (FRBR) .......................................................................... 509
15.3.3 Transmitter Shift Register (FTSR)........................................................................ 509
15.3.5 Divisor Latch H, L (FDLH, FDLL) ...................................................................... 510
Rev. 1.00 Mar. 12, 2008 Page xvii of xIviii