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(3)
16-Bit, 2-State Access Space
Figures 6.7 to 6.9 show bus timings for a 16-bit, 2-state access space. When a 16-bit access space
is accessed, the upper half (D15 to D8) of the data bus is used for even addresses, and the lower
half (D7 to D0) for odd addresses. Wait states cannot be inserted.
Read
Write
Note: * For external address space access, this signal is not output when the 256-Kbyte extended area
is accessed with CS256E = 1.
Figure 6.7 Bus Timing for 16-Bit, 2-State Access Space (Even Byte Access)
φ
Address bus
IOS (IOSE = 1)
CS256 (CS256E = 1)
AS (IOSE = 0)
*
RD
D15 to D8
D7 to D0
HWR
LWR
D15 to D8
D7 to D0
Section 6 Bus Controller (BSC)
Bus cycle
T
T
1
2
Invalid
High level
Valid
Undefined
Rev. 1.00 Mar. 12, 2008 Page 131 of 1178
Valid
REJ09B0403-0100
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