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22.8.4
DTC Transfer End Interrupt
When the DTC transfer end interrupt is generated, handle the processing below.
(1)
Endpoint 1
• Clear the EP1DMAE bit in DMA to 0.
• Write H'BF to the IFR0 register.
Write 0 to the EP1FULL bit. The bit manipulation instruction should not be used for this
setting.
When the DTC transfer is continuously performed:
• Set CRA and CRB of the DTC the number of transfers.
• Set the DTCERF register.
• Set 1 to the EP1DMAE bit in DMA.
(2)
Endpoint 2
• Clear the EP2DMAE bit in DMA to 0.
• Write H'EF to the IFR0 register.
Write 0 to the EP2EMPTY bit. The bit manipulation instruction should not be used for this
setting.
When the DTC transfer is continuously performed:
• Set CRA and CRB of the DTC the number of transfers.
• Set the DTCERF register.
• Set 1 to the EP2DMAE bit in DMA.
Section 22 USB Function Module (USB)
Rev. 1.00 Mar. 12, 2008 Page 889 of 1178
REJ09B0403-0100
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