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15.3.9
Line Control Register (FLCR)
FLCR sets formats of the transmit/receive data.
Bit
Bit Name
7
DLAB
6
BREAK
5
STICK
PARITY
4
EPS
3
PEN
Initial Value
R/W Description
0
R/W Divisor Latch Address
0
R/W Break Control
0
R
0
R/W Parity Select
0
R/W Parity Enable
Section 15 Serial Communication Interface with FIFO (SCIF)
FDLL and FDLH are placed at the same addresses as
the FRBR/FTHR and FIER addresses. This bit selects
which register is to be accessed.
0: FRBR/FTHR and FIER access enabled
1: FDLL and FDLH access enabled
Generates a break by driving the serial output signal
TxDF low.
The break state is released by clearing this bit.
0: Break released
1: Break generated
Stick Parity
This bit is not supported in this LSI.
This bit is always read as 0. The initial value should
not be changed.
Selects even or odd parity when the PEN bit is 1.
0: Odd parity
1: Even parity
Selects whether to add a parity bit for data
transmission and whether to perform a parity check for
data reception.
0: No parity bit added/parity check disabled
1: Parity bit added/parity check enabled
Rev. 1.00 Mar. 12, 2008 Page 515 of 1178
REJ09B0403-0100
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