Timing Of Counter Clear At Compare-Match - Renesas H8S Family Hardware Manual

11.3.3

Timing of Counter Clear at Compare-Match

TCNT is cleared when compare-match A or compare-match B occurs, depending on the setting of
the CCLR1 and CCLR0 bits in TCR. Figure 11.5 shows the timing of clearing the counter by a
compare-match.
φ
Compare-match
signal
TCNT
Figure 11.5 Timing of Counter Clear by Compare-Match
11.3.4 Timing of Overflow Flag (OVF) Setting
The OVF bit in TCSR is set to 1 when the TCNT overflows (changes from H'FF to H'00). Figure
11.6 shows the timing of OVF flag setting.
φ
TCNT
Overflow signal
OVF
N
H'FF
Figure 11.6 Timing of OVF Flag Setting
Section 11 8-Bit Timer (TMR)
H'00
H'00
Rev. 1.00 Mar. 12, 2008 Page 405 of 1178
REJ09B0403-0100