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20.3.4
PHY Interface Register (PIR)
PIR is a 32-bit readable/writable register that provides a means of accessing the PHY registers via
the RMII.
Bit
Bit Name
31 to 4
3
MDI
2
MDO
1
MMD
0
MDC
Initial
Value
R/W Description
All 0
R
Reserved
These bits are always read as 0. The initial value
should not be changed.
Undefined R
MII Management Data-In
Indicates the level of the MDIO pin.
0
R/W MII Management Data-Out
Outputs the value set to this bit from the MDIO pin,
when the MMD bit is 1.
0
R/W MII Management Mode
Specifies the data read/write direction with respect to
the MII.
0: Read direction is indicated
1: Write direction is indicated
0
R/W MII Management Data Clock
Outputs the value set to this bit from the MDC pin and
supplies the MII with the management data clock. For
the method of accessing the MII registers, see section
20.4.4, Accessing MII Registers.
Section 20 Ethernet Controller (EtherC)
Rev. 1.00 Mar. 12, 2008 Page 767 of 1178
REJ09B0403-0100
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