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18.3.9
I
C SMBus Control Register (ICSMBCR)
ICSMBCR is used to support the System Management Bus (SMBus) specifications. To support
the SMBus specification, SDA output data hold time should be specified in the range of 300 ns to
1000 ns. Table 18.7 shows the relationship between the ICSMBCR setting and output data hold
time.
When the SMBus is not supported, the initial value should not be changed. ICSMBCR is enabled
to access when bit MSTP4 is cleared to 0.
Bit
Bit Name
7
SMB5E
6
SMB4E
5
SMB3E
4
SMB2E
3
SMB1E
2
SMB0E
1
FSEL1
0
FSEL0
Initial
Value
R/W
Description
0
R/W
SMBus Enable
0
R/W
These bits enable/disable to support the SMBus, in
combination with bits FSEL1 and FSEL0. Bits SMB5E,
0
R/W
SMB4E, SMB3E, SMB2E, SMB1E, and SMB0E control
0
R/W
IIC_5, IIC_4, IIC_3, IIC_2, IIC_1, and IIC_0, respectively.
0
R/W
0: Disables to support the SMBus
00
R/W
1: Enables to support the SMBus
0
R/W
Frequency Selection
0
R/W
These bits must be specified to match the system clock
frequency in order to support the SMBus. For details of the
setting, see table 18.6.
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Section 18 I
C Bus Interface (IIC)
Rev. 1.00 Mar. 12, 2008 Page 615 of 1178
REJ09B0403-0100
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