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Section 8 I/O Ports
• PA5/ExIRQ5/EVENT5/WOL
The pin function is switched as shown below according to and the PA5DDR bit.
Setting the ISS5 bit in ISSR makes the pin to function as the ExIRQ5 input pin.
When using this pin as the ExIRQ5 input or EVENT5 input pin, clear the PA5DDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PA5DDR bit to 1 to use
the pin as the PA5 output pin.
When the module stop mode is cleared in both the EtherC, and E-DMAC, this pin functions as
the WOL input pin.
PA5DDR
Pin function
ExIRQ5 input pin/EVENT5 input pin
• PA4/ExIRQ4/EVENT4, PA3/ExIRQ3/EVENT3, PA2/ExIRQ2/EVENT2,
PA1/ExIRQ1/EVENT1, PA0/ExIRQ0/EVENT0
The pin function is switched as shown below according to the PAnDDR bit.
Setting the ISSn bit in ISSR makes the pin to function as the ExIRQn input pin.
When using this pin as the ExIRQn input or EVENTn input pin, clear the PAnDDR bit to 0.
Though the settings for the EVENT input pin have been made, set the PAnDDR bit to 1 to use
the pin as the PAn output pin.
PAnDDR
Pin function
ExIRQn input pin/EVENTn input pin
[Legend]
n = 4 to 0
Rev. 1.00 Mar. 12, 2008 Page 244 of 1178
REJ09B0403-0100
0
PA5 input pin
0
PAn input pin
1
PA5 output pin
1
PAn output pin
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