Renesas H8S Family Hardware Manual page 801

Table 19.13 HIRQ Setting and Clearing Conditions when SCIF Channels are Used
Host Interrupt Setting Condition
SMI
The SCIF interrupt corresponding to the
HIRQi
host interrupt request selected by
(i = 1, 3 to 15)
SIRQCR3 occurs.
Write 1 to IRQ1E1
No
No
Figure 19.12 HIRQ Flowchart (Example of Channel 1)
Slave CPU
ODR1 write
SERIRQ IRQ1 output
OBF1 = 0?
Yes
All bytes
transferred?
Yes
Clearing Condition
Relevant SCIF interrupt is cleared
SERIRQ IRQ1
source clear
Rev. 1.00 Mar. 12, 2008 Page 753 of 1178
Section 19 LPC Interface (LPC)
Master CPU
Interrupt initiation
ODR1 read
Hardware operation
Software operation
REJ09B0403-0100