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Pin Functions
• PB7/EVENT15/RM_RX-ER, PB6/EVENT14/RM_CRS-DV, PB5/EVENT13/RM_REF-CLK
PB4/EVENT12/RM_TX-EN
The pin function is switched as shown below according to the PBnDDR bit. When using this
pin as the EVENT input pin, clear the PBnDDR bit to 0. These pins can be used as EtherC I/O
pins when the EtherC is enabled.
EtherC,
E-DMAC
PBnDDR
Event
Disabled
counter
Pin
PBn input pin
function
[Legend]
n = 7 to 4, m = 15 to 12, X: Don't care.
Note:
*
See section 7.3, DTC Event Counter, for the event counter settings.
• PB3/EVENT11/DB3/RM_RXD1, PB2/EVENT10/DB2/RM_RXD0,
PB1/EVENT9/DB1/RM_TXD1, PB0/EVENT8/DB0/RM_TXD0
The pin function is switched as shown below according to the combination of the module stop
state in the EtherC, E-DMAC, the PBnDDR bit and the PBnNCE bit.
EtherC,
E-DMAC
PBnDDR
Event
Disabled
counter
PBnNCE
0
Pin
PBn input pin
function
[Legend]
n = 3 to 0, m = 11 to 8, X: Don't care.
Either of them is stopped
0
Enabled
EVENTm input
pin
Either of them is stopped
0
Enabled
1
X
EVENTm input
pin
1
X
PBn output pin
1
X
X
PBn output pin
Rev. 1.00 Mar. 12, 2008 Page 251 of 1178
Section 8 I/O Ports
Both of then are
stopped
X
X
RM_xxxx
EtherC I/O pin
Both of then are
stopped
X
X
X
RM_xxxx
EtherC I/O pin
REJ09B0403-0100
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