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• PE2/LAD2
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE2DDR bit.
LPC
PE2DDR
Pin function
[Legend]
X: Don't care.
• PE1/LAD1
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE1DDR bit.
LPC
PE1DDR
Pin function
[Legend]
X: Don't care.
• PE0/LAD0
The pin function is switched as shown below according to whether the LPC is enabled or
disabled and the PE0DDR bit.
LPC
PE0DDR
Pin function
[Legend]
X: Don't care.
Disabled
0
PE2 input pin
Disabled
0
PE1 input pin
Disabled
0
PE0 input pin
1
PE2 output pin
1
PE1 output pin
1
PE0 output pin
Rev. 1.00 Mar. 12, 2008 Page 265 of 1178
Section 8 I/O Ports
Enabled
X
LAD2 input/output pin
Enabled
X
LAD1 input/output pin
Enabled
X
LAD0 input/output pin
REJ09B0403-0100
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