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Section 18 I
C Bus Interface (IIC)
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9. Note on when I
C bus interface stop condition instruction is issued
In a situation where the rise time of the 9th clock of SCL exceeds the stipulated value because
of a large bus load capacity or where a slave device in which a wait can be inserted by driving
the SCL pin low is used, the stop condition instruction should be issued after reading SCL after
the rise of the 9th clock pulse and determining that it is low.
SCL
SDA
IRIC
Note: This restriction on usage can be canceled by setting the FNC1 and FNC0 bits to B'11 in
ICXR.
10. Note on IRIC flag clear when the wait function is used
When the wait function is used in I
rise time of SCL exceeds the stipulated value or where a slave device in which a wait can be
inserted by driving the SCL pin low is used, the IRIC flag should be cleared after determining
that the SCL is low.
If the IRIC flag is cleared to 0 when WAIT = 1 while the SCL is extending the high level time,
the SDA level may change before the SCL goes low, which may generate a start or stop
condition erroneously.
Rev. 1.00 Mar. 12, 2008 Page 658 of 1178
REJ09B0403-0100
Secures a high period
9th clock
VIH
SCL is detected as low
because the rise of the
waveform is delayed
[1] SCL = low determination
Figure 18.31 Stop Condition Issuance Timing
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C bus interface master mode and in a situation where the
Stop condition generation
[2] Stop condition instruction issuance
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