Advertisement
Section 8 I/O Ports
(c)
Single-Chip Mode
The relationship between register setting values and pin functions are as follows.
• P47 to P44
The pin function is switched as shown below according to the P4nDDR bit and the P4nNCE bit.
When the ISSn bit in ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is
set to 1, the pin can be used as the IRQn input pin. To use as the IRQn input pin, clear the
P4nDDR bit to 0.
P4nDDR
P4nNCE
Pin function
[Legend] n = 7 to 4
X: Don't care.
The pin function is switched as shown below according to the P4nDDR bit. When the ISSn bit in
ISSR is cleared to 0 and the IRQnE bit in IER of the interrupt controller is set to 1, the pin can be
used as the IRQn input pin. To use as the IRQn input pin, clear the P4nDDR bit to 0.
• P43 to P40
P4nDDR
Pin function
[Legend] n = 3 to 0
Rev. 1.00 Mar. 12, 2008 Page 212 of 1178
REJ09B0403-0100
0
0
P4n input
IRQn input
(with the noise canceler)
0
P4n input pin
IRQn input pin
1
DBn input
IRQn input
1
X
P4n output
1
P4n output pin
Advertisement
