Section 20 Ethernet Controller (Etherc) - Renesas H8S Family Hardware Manual

Section 20 Ethernet Controller (EtherC)

This LSI has an on-chip Ethernet controller (EtherC) conforming to the Ethernet or the IEEE802.3

MAC (Media Access Control) layer standard. Connecting a physical-layer LSI (PHY-LSI)

complying with this standard enables the Ethernet controller (EtherC) to perform transmission and

reception of Ethernet/IEEE802.3 frames. This LSI has one MAC layer interface.

The Ethernet controller is connected to the direct memory access controller for Ethernet controller

(E-DMAC) inside this LSI, and carries out high-speed data transfer to and from the memory.

• Transmission and reception of Ethernet/IEEE802.3 frames

• Supports 10/100 Mbps receive/transfer

• Supports full-duplex and half-duplex modes

• Conforms to IEEE802.3u standard RMII (Reduced Media Independent Interface)

• Magic Packet detection and Wake-On-LAN (WOL) signal output

• Conforms to IEEE802.3x flow control

Note: The EtherC operates only in high-speed mode.

Figure 20.1 shows the configuration of the EtherC.

Rev. 1.00 Mar. 12, 2008 Page 757 of 1178

REJ09B0403-0100