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Section 19 LPC Interface (LPC)
19.3.30 BT Data Buffer (BTDTR)
BTDTR is used to implement the BT mode. BTDTR consists of two FIFOs: the host write transfer
FIFO and the host read transfer FIFO. Their capacities are 64 bytes each. When using BTDTR,
enable FIFO by means of the bits FSEL0 and FSEL1.
Initial
Bit
Bit Name
Value
7 to 0 bit7 to bit0 Undefined R/W
19.3.31 BT Interrupt Mask Register (BTIMSR)
BTIMSR is one of the registers used to implement BT mode. The BTIMSR register contains the
bits used to control the interrupts to the host.
Initial
Bit
Bit Name
Value
7
BMC_
0
HWRST
6
0
5
0
Rev. 1.00 Mar. 12, 2008 Page 730 of 1178
REJ09B0403-0100
R/W
Slave Host Description
R/W
The data written by the host is stored in FIFO (64
bytes) for host write transfer and read out by the
slave in order of host writing. The data written by the
slave is stored in FIFO (64 bytes) for host read
transfer and read out by the host in order of slave
writing.
R/W
Slave
Host
Description
2
1
R/(W)*
R/(W)*
Slave Reset
Performs a reset from the host to the slave. The
host can only write a 1. Writing a 0 to this bit is
invalid. The host will always return a 0 on read
out. Setting the RSTRENBL bit enables a 1 to be
read from the host.
0: The reset is cancelled
[Clearing condition]
When the slave writes a 0, after a 1 has been
read from BMC_HWRST.
1: The reset is in progress.
[Setting condition]
When the host writes a 1.
R/W
R/W
Reserved
R/W
R/W
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