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Figure 7.7 Memory Mapping in Block Transfer Mode............................................................... 178
Figure 7.8 Chain Transfer Operation .......................................................................................... 179
Figure 7.9 DTC Operation Timing (Example in Normal Mode or Repeat Mode)...................... 180
Figure 7.10 DTC Operation Timing (Example of Block Transfer Mode,
with Block Size of 2) .............................................................................................. 181
Figure 7.11 DTC Operation Timing (Example of Chain Transfer) ............................................ 181
Section 8 I/O Ports
Figure 8.1 Noise Canceler Circuit .............................................................................................. 203
Figure 8.2 Noise Canceler Operation.......................................................................................... 204
Figure 8.3 Noise Canceler Circuit .............................................................................................. 210
Figure 8.4 Noise Canceler Operation.......................................................................................... 210
Figure 8.5 Noise Canceler Circuit .............................................................................................. 249
Figure 8.6 Noise Canceler Operation.......................................................................................... 250
Figure 8.7 Noise Canceler Circuit .............................................................................................. 286
Figure 8.8 Noise Canceler Operation.......................................................................................... 287
Figure 8.9 Noise Canceler Circuit .............................................................................................. 293
Figure 8.10 Noise Canceler Operation........................................................................................ 293
Figure 8.11 Noise Canceler Circuit ............................................................................................ 333
Figure 8.12 Noise Canceler Operation........................................................................................ 334
Section 9 14-Bit PWM Timer (PWMX)
Figure 9.1 PWMX (D/A) Block Diagram................................................................................... 357
Figure 9.2 PWMX (D/A) Operation ........................................................................................... 365
Figure 9.3 Output Waveform (OS = 0, DADR corresponds to T
Figure 9.4 Output Waveform (OS = 1, DADR corresponds to T
Figure 9.5 D/A Data Register Configuration when CFS = 1 ...................................................... 369
Figure 9.6 Output Waveform when DADR = H'0207 (OS = 1) ................................................. 370
Section 10 16-Bit Free-Running Timer (FRT)
Figure 10.1 Block Diagram of 16-Bit Free-Running Timer ....................................................... 374
Figure 10.2 Increment Timing with Internal Clock Source ........................................................ 381
Figure 10.3 Timing of Output Compare A Output ..................................................................... 381
Figure 10.4 Clearing of FRC by Compare-Match A Signal ....................................................... 382
Figure 10.5 Timing of Output Compare Flag (OCFA or OCFB) Setting ................................... 382
Figure 10.6 Timing of Overflow Flag (OVF) Setting................................................................. 383
Figure 10.7 OCRA Automatic Addition Timing ........................................................................ 384
Figure 10.8 Conflict between FRC Write and Clear................................................................... 385
Figure 10.9 Conflict between FRC Write and Increment ........................................................... 386
Figure 10.10 Conflict between OCR Write and Compare-Match
(When Automatic Addition Function is Not Used) .............................................. 387
) ............................................ 368
L
) ............................................ 369
H
Rev. 1.00 Mar. 12, 2008 Page xxxi of xIviii
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