Renesas H8S Family Hardware Manual page 258

Section 8 I/O Ports
∆t
Latch
Pin input
Sampling clock
P4n input
1 expected
P4nDR
0 expected
P4nDR
(n = 7 to 4)
Rev. 1.00 Mar. 12, 2008 Page 210 of 1178
REJ09B0403-0100
φ/2, φ/32, φ/512, φ/8192,
φ/32768, φ/65536,
φ/131072, φ/262144
Sampling clock selection
Latch Latch
Figure 8.3 Noise Canceler Circuit
Figure 8.4 Noise Canceler Operation
Match
detection
Port data
circuit
register