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2
6. The I
C bus interface specifications for the SCL and SDA rise and fall times are under 1000 ns
and 300 ns. The I
table 18.11. However, because of the rise and fall times, the I
may not be satisfied at the maximum transfer rate. Table 18.13 shows output timing
calculations for different operating frequencies, including the worst-case influence of rise and
fall times.
t
fails to meet the I
BUFO
to provide coding to secure the necessary interval (approximately 1 µs) between issuance of a
stop condition and issuance of a start condition, or (b) to select devices whose input timing
permits this output timing for use as slave devices connected to the I
t
in high-speed mode and t
SCLLO
specifications for worst-case calculations of t
investigated include (a) adjusting the rise and fall times by means of a pull-up resistor and
capacitive load, (b) reducing the transfer rate to meet the specifications, or (c) selecting devices
whose input timing permits this output timing for use as slave devices connected to the I
bus.
2
C bus interface SCL and SDA output timing is prescribed by t
2
C bus interface specifications at any frequency. The solution is either (a)
in standard mode fail to satisfy the I
STASO
Section 18 I
2
C bus interface specifications
/t
. Possible solutions that should be
Sr
Sf
Rev. 1.00 Mar. 12, 2008 Page 653 of 1178
2
C Bus Interface (IIC)
, as shown in
cyc
2
C bus.
2
C bus interface
2
C
REJ09B0403-0100
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