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Section 19 LPC Interface (LPC)
An LPC transfer cycle is started when the LFRAME signal goes low in the bus idle state. If the
LFRAME signal goes low when the bus is not idle, this means that a forced termination (abort) of
the LPC transfer cycle has been requested.
In an I/O read cycle or I/O write cycle, transfer is carried out using LAD3 to LAD0 in the
following order, in synchronization with LCLK. The host can be made to wait by sending back a
value other than B'0000 in the slave's synchronization return cycle, but the LPC interface of this
LSI always returns B'0000 (except for the BT interface).
If the received address matches the host address for an LPC register, the LPC interface enters the
busy state; it returns to the idle state by output of a state count 12 turnaround. Register and flag
changes are made at this timing, so in the event of a transfer cycle forced termination (abort),
registers and flags are not changed.
The timing of the LFRAME, LCLK, and LAD signals is shown in figures 19.2 and 19.3.
Table 19.5 LPC I/O Cycle
State
Count
Contents
1
Start
2
Cycle type/direction
3
Address 1
4
Address 2
5
Address 3
6
Address 4
7
Turnaround (recovery) Host
8
Turnaround
9
Synchronization
10
Data 1
11
Data 2
12
Turnaround (recovery) Slave
13
Turnaround
Rev. 1.00 Mar. 12, 2008 Page 734 of 1178
REJ09B0403-0100
I/O Read Cycle
Drive
Value
Source
(3 to 0)
Host
0000
Host
0000
Host
Bits 15 to 12
Host
Bits 11 to 8
Host
Bits 7 to 4
Host
Bits 3 to 0
1111
None
ZZZZ
Slave
0000
Slave
Bits 3 to 0
Slave
Bits 7 to 4
1111
None
ZZZZ
I/O Write Cycle
Contents
Start
Cycle type/direction
Address 1
Address 2
Address 3
Address 4
Data 1
Data 2
Turnaround (recovery) Host
Turnaround
Synchronization
Turnaround (recovery) Slave
Turnaround
Drive
Value
Source
(3 to 0)
Host
0000
Host
0010
Host
Bits 15 to 12
Host
Bits 11 to 8
Host
Bits 7 to 4
Host
Bits 3 to 0
Host
Bits 3 to 0
Host
Bits 7 to 4
1111
None
ZZZZ
Slave
0000
1111
None
ZZZZ
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