Advertisement
• STR3 (TWRE = 0 and SELSTR3 = 1)
Bit
Bit Name Initial Value Slave Host Description
7
DBU37
0
6
DBU36
0
5
DBU35
0
4
DBU34
0
3
C/D3
0
2
DBU32
0
1
IBF3A
0
R/W
R/W
R
Defined by User
R/W
R
The user can use these bits as necessary.
R/W
R
R/W
R
R
R
Command/Data Flag
When the host writes to IDR3, bit 2 of the I/O
address is written into this bit to indicate whether
IDR3 contains data or a command.
0: Content of input data register (IDR3) is a data
1: Content of input data register (IDR3) is a
command
R/W
R
Defined by User
The user can use this bit as necessary.
R
R
Input Data Register Full
Indicates whether or not there is receive data in
IDR3. This bit is an internal interrupt source to the
slave (this LSI).
0: There is not receive data in IDR3
[Clearing condition]
When the slave reads IDR3
1: There is receive data in IDR3
[Setting condition]
When the host writes to IDR3 in an I/O write cycle
Section 19 LPC Interface (LPC)
Rev. 1.00 Mar. 12, 2008 Page 697 of 1178
REJ09B0403-0100
Advertisement
