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System Control Register 2 (Syscr2) - Renesas H8S Family Hardware Manual

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• When ADMXE = 0
Bit
Bit Name
2 to 0
• When ADMXE = 1
Bit
Bit Name
2
WC22
1, 0
6.3.5

System Control Register 2 (SYSCR2)

SYSCR2 controls the address-data multiplex operation.
Bit
Bit Name
7 to 4 
3
ADMXE
2 to 0 
Initial
Value
R/W
Description
All 1
R/W
Reserved
Initial
Value
R/W
Description
1
R/W
Address-Data Multiplex Extended Area Address Cycle
Wait Count 2
Selects the number of program wait states to be inserted
into the address cycle for access to the address-data
multiplex extended area.
0: Program wait state is not inserted
1: 1 program wait state is inserted in the address cycle
All 1
R/W
Reserved
Initial Value
R/W
All 0
R/W
0
R/W
All 0
R/W
Description
Reserved
The initial value should not be changed.
Address-Data Multiplex Bus Interface Enable
0: Normal extended bus interface
1: Address data multiplex extended bus interface
Reserved
The initial value should not be changed.
Rev. 1.00 Mar. 12, 2008 Page 115 of 1178
Section 6 Bus Controller (BSC)
REJ09B0403-0100

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This manual is also suitable for:

R4f2472R4f2462H8s/2462H8s/2400 seriesH8s/2472