Smic Flag Register (Smicflg) - Renesas H8S Family Hardware Manual

19.3.20 SMIC Flag Register (SMICFLG)

SMICFLG is one of the registers used to implement SMIC mode. This register includes bits that
indicate whether or not the system is ready to data transfer and those that are used for handshake
of the transfer cycles.
Bit Bit Name
7 RX_DATA_RDY
6 TX_DATA_RDY

5
4 SMI
3 SEVT_ATN
2 SMS_ATN
R/W
Initial Value Slave Host Description
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
0 R/W
R Read Transfer Ready
Indicates whether or not the slave is ready for
the host read transfer.
0: Slave waits for ready status
1: Slave is ready for the host read transfer
R Write Transfer Ready
Indicates whether or not the slave is ready for
the host next write transfer.
0: The slave waits for ready status
1: The slave is ready for the host write
transfer.
R Reserved
The initial value should not be changed.
R SMI Flag
This bit indicates that the SMI is asserted.
0: Indicates waiting for SMI assertion
1: Indicates SMI assertion
R Event Flag
When the slave detects an event for the host,
this bit is set.
0: Indicates waiting for event detection
1: Indicates event detection
R SMS Flag
When there is a message to be transmitted
from the slave to the host, this bit is set.
0: There is not a message
1: There is a message
Rev. 1.00 Mar. 12, 2008 Page 713 of 1178
Section 19 LPC Interface (LPC)
REJ09B0403-0100