Fifo Depth Register (Fdr) - Renesas H8S Family Hardware Manual

Section 21 Ethernet Controller Direct Memory Access Controller (E-DMAC)

21.2.11 FIFO Depth Register (FDR)

FDR is a 32-bit readable/writable register that specifies the capacity of the transmit and receive
FIFOs.
Bit Bit Name

31 to 11
10 to 8 TFD2 to
TFD0

7 to 3
2 to 0 RFD2 to
RFD0
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REJ09B0403-0100
Initial
value R/W Description
All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
B'000 R Transmit FIFO Capacity
Specify the capacity of transmit FIFO, from 256 bytes
to 2048 bytes, in 256-byte units. The set value should
not be changed after the transmit/receive operation is
started.
All 0 R Reserved
These bits are always read as 0. The initial value
should not be changed.
B'000 R Receive FIFO Capacity
Specify the capacity of receive FIFO, from 256 bytes
to 2048 bytes, in 256-byte units. The set value should
not be changed after the transmit/receive operation is
started.