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12.2
Input/Output Pins
The WDT has the pins listed in table 12.1.
Table 12.1 Pin Configuration
Name
Reset output pin
External sub-clock input
pin
12.3
Register Descriptions
The WDT has the following registers. To prevent accidental overwriting, TCSR and TCNT have
to be written to in a method different from normal registers. For details, see section 12.6.1, Notes
on Register Access. For details on the system control register, see section 3.2.2, System Control
Register (SYSCR).
• Timer counter (TCNT)
• Timer control/status register (TCSR)
12.3.1
Timer Counter (TCNT)
TCNT is an 8-bit readable/writable up-counter. TCNT is initialized to H'00 when the TME bit in
timer control/status register (TCSR) is cleared to 0.
Symbol
I/O
RESO
Output
EXCL
Input
Section 12 Watchdog Timer (WDT)
Function
Outputs the counter overflow signal in
watchdog timer mode
Inputs the clock pulses to the WDT_1
prescaler counter
Rev. 1.00 Mar. 12, 2008 Page 415 of 1178
REJ09B0403-0100
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