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17.4.7
Clock Synchronous Communication Mode
In clock synchronous communication mode, data communications are performed via three lines:
clock line (SSCK), data input line (SSI), and data output line (SSO).
(1)
Initial Settings in Clock Synchronous Communication Mode
Figure 17.12 shows an example of the initial settings in clock synchronous communication mode.
Before data transfer, clear both the TE and RE bits in SSER to 0 to set the initial values.
Note: Before changing operating modes and communications formats, clear both the TE and RE
bits to 0. Although clearing the TE bit to 0 sets the TDRE bit to 1, clearing the RE bit to 0
does not change the values of the RDRF and ORER bits and SSRDR. Those bits retain the
previous values.
Start setting initial values
Clear TE and RE bits in SSER to 0
[1]
Set a bit in ICR to 1
[2]
Specify MSS and SCKS in SSCRH
Set SSUMS in SSCRL to 1 and
[3]
specify bits DATS1 and DATS0
Specify CPOS, CKS2, CKS1, and
[4]
CKS0 bits in SSMR
Specify TEIE, TIE, RIE,
[5]
and CEIE bits in SSER
Figure 17.12 Example of Initial Settings in Clock Synchronous Communication Mode
Section 17 Synchronous Serial Communication Unit (SSU)
[1] When the pin is used as an input.
[2] Specify master/slave mode selection and SSCK pin
[3] Selects clock synchronous communication mode and
[4] Specify clock polarity selection and transfer clock rate
[5] Enables/disables interrupt request to the CPU.
End
selection.
specify transmit/receive data length.
selection.
Rev. 1.00 Mar. 12, 2008 Page 577 of 1178
REJ09B0403-0100
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