Register Descriptions - Renesas H8S Family Hardware Manual

Section 15 Serial Communication Interface with FIFO (SCIF)

15.3

The SCIF has the following registers. The register configuration of the SCIF is shown below.

Access to the registers is switched by the SCIFE bit in HICR5 and bit 3 in SUBMSTPBL. For

details, see table 15.2. For the SCIF address registers H and L (SCIFADRH, SCIFADRL) and

SERIRQ control register 4 (SIRQCR4), see section 19, LPC Interface (LPC).

• Host interface control register 5 (HICR5)

• Sub-chip module stop control register AL (SUBMSTPAH)

• Receive buffer register (FRBR)

• Transmitter holding register (FTHR)

• Divisor latch L (FDLL)

• Interrupt enable register (FIER)

• Divisor latch H (FDLH)

• Interrupt identification register (FIIR)

• FIFO control register (FFCR)

• Line control register (FLCR)

• Modem control register (FMCR)

• Line status register (FLSR)

• Modem status register (FMSR)

• Scratch pad register (FSCR)

• SCIF control register (SCIFCR)

• SCIF address register H (SCIFADRH)

• SCIF address register L (SCIFADRL)

• Serial IRQ control register 4 (SIRQCR4)

Table 15.2 Register Access

SCIFE Bit in HICR5

Bit 3 in SUBMSTPBL 0

Other than SCIFCR

Notes: 1. When LPC access is set, writing from the H8S CPU is disabled. The read value is H'FF.

2. When H8S CPU access is set, writing from the LPC is disabled. The read value is H'00.

Rev. 1.00 Mar. 12, 2008 Page 508 of 1178

REJ09B0403-0100

Access disabled H8S CPU

Access disabled LPC access*

Access disabled