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Section 20 Ethernet Controller (EtherC)
Bit
Bit Name
16
TXF
15 to 13
12
PRCEF
11, 10
9
MPDE
8, 7
6
RE
Rev. 1.00 Mar. 12, 2008 Page 762 of 1178
REJ09B0403-0100
Initial
Value
R/W
0
R/W
All 0
R
0
R/W
All 0
R
0
R/W
All 0
R
0
R/W
Description
Transmit Flow Control Operating mode
0: Transmit flow control function is disabled
(automatic PAUSE frames are not transmitted)
1: Transmit flow control function is enabled
(automatic PAUSE frame is transmitted as
necessary)
Reserved
These bits are always read as 0. The initial value
should not be changed.
Permit Receive CRC Error Frame
0: A frame with a CRC error is received as a frame
with an error.
1: A frame with a CRC error is received as a frame
without an error. The CEFCR register is therefore
not incremented.
If this bit is clear and a frame with an error is received,
a CRC error is reflected in ECSR of the E-DMAC and
the status of the receive descriptor. If this bit is set to
1, a frame with an error is received as a normal frame.
Reserved
These bits are always read as 0. The initial value
should not be changed.
Magic Packet Detection Enable
Enables or disables Magic Packet detection by
hardware to allow activation from the Ethernet.
0: Magic Packet detection is not enabled
1: Magic Packet detection is enabled
Reserved
These bits are always read as 0. The initial value
should not be changed.
Reception Enable
0: Receive function is disabled
1: Receive function is enabled
If this bit is changed from enabling to disabling while a
frame is being received, the receive function remains
enabled until reception of the frame is completed.
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