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φ
WAIT
Address bus
IOS (IOSE = 1)
AS (IOSE = 0)
*
RD
Read
Data bus
WR
Write
Data bus
Note: ↓ shown in φ clock indicates the WAIT pin sampling timing.
* For external address space access, this signal is not output when the 256-kbyte extended area
is accessed with CS256E = 1.
Figure 6.28 Example of Wait State Insertion Timing (Pin Wait Mode)
By program wait
T
T
T
1
2
W
Section 6 Bus Controller (BSC)
By WAIT pin
T
T
W
W
Read data
Write data
Rev. 1.00 Mar. 12, 2008 Page 149 of 1178
T
3
REJ09B0403-0100
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