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Section 17 Synchronous Serial Communication Unit (SSU)
Bit
Bit Name
3
SCSATS
2
SSODTS
1, 0
17.3.7
SS Transmit Data Registers 0 to 3 (SSTDR0 to SSTDR3)
SSTDR is an 8-bit register that stores transmit data. When 8-bit data length is selected by bits
DATS1 and DATS0 in SSCRL, SSTDR0 is valid. When 16-bit data length is selected, SSTDR0
and SSTDR1 are valid. When 32-bit data length is selected, SSTDR0 to SSTDR3 are valid.
When the SSU detects that SSTRSR is empty, it transfers the transmit data written in SSTDR to
SSTRSR and starts serial transmission. If the next transmit data has already been written to
SSTDR during serial transmission, the SSU performs consecutive serial transmission.
Although SSTDR can always be read from or written to by the CPU and DMAC, to achieve
reliable serial transmission, write transmit data to SSTDR after confirming that the TDRE bit in
SSSR is set to 1.
Rev. 1.00 Mar. 12, 2008 Page 562 of 1178
REJ09B0403-0100
Initial
Value
R/W
0
R/W
0
R/W
All 0
R/W
Description
Selects the assertion timing of the SCS pin (valid in
SSU and master mode).
0: Min. values of t
LEAD
1: Min. values of t
LEAD
Selects the data output timing of the SSO pin (valid in
SSU and master mode)
0: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
1: While BIDE = 0, MSS = 1, and TE = 1 or while BIDE
= 1, TE = 1, and RE = 0, the SSO pin outputs data
while the SCS pin is driven low
Reserved
These bits are always read as 0. The initial value
should not be changed.
are 1/2 × t
and t
LAG
SUcyc
are 3/2 × t
and t
LAG
SUcyc
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