Dtc Transfer Count Register A (Cra) - Renesas H8S Family Hardware Manual

Section 7 Data Transfer Controller (DTC)

DTC Transfer Count Register A (CRA)

CRA is a 16-bit register that designates the number of times data is to be transferred by the DTC.

In normal mode, the entire CRA functions as a 16-bit transfer counter (1 to 65536). It is

decremented by 1 every time data is transferred, and transfer ends when the count reaches H'0000.

In repeat mode or block transfer mode, the CRA is divided into two parts; the upper eight bits

(CRAH) and the lower 8 bits (CRAL). CRAH holds the number of transfers while CRAL

functions as an 8-bit transfer counter (1 to 256). CRAL is decremented by 1 every time data is

transferred, and the contents of CRAH are sent when the count reaches H'00.

DTC Transfer Count Register B (CRB)

CRB is a 16-bit register that designates the number of times data is to be transferred by the DTC in

block transfer mode. It functions as a 16-bit transfer counter (1 to 65536) that is decremented by 1

every time data is transferred, and transfer ends when the count reaches H'0000.

DTC Enable Registers (DTCER)

DTCER specifies DTC activation interrupt sources. DTCER is comprised of five registers:

DTCERA to DTCERF. The correspondence between interrupt sources and DTCE bits is shown in

tables 7.1 and 7.4. For DTCE bit setting, use bit manipulation instructions such as BSET and

BCLR. Multiple DTC activation sources can be set at one time (only at the initial setting) by

masking all interrupts and writing data after executing a dummy read on the relevant register.

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REJ09B0403-0100

DTC Activation Enable

Setting this bit to 1 specifies a relevant interrupt source

as a DTC activation source.

[Clearing conditions]

When data transfer has ended with the DISEL bit in

MRB set to 1

When the specified number of transfers have ended

These bits are not cleared when the DISEL bit is 0 and

the specified number of transfers have not been