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Section 15 Serial Communication Interface with FIFO (SCIF)
(3)
Serial Data Reception
Figure 15.5 shows an example of the data reception flowchart.
Read DR flag in FLSR
No
No
No
(End of reception or reception standby)
Rev. 1.00 Mar. 12, 2008 Page 530 of 1178
REJ09B0403-0100
Initialization
Start reception
DR = 1
Yes
Read FLSR
RXFIFOERR = 1,
Yes
BI = 1, FE = 1,
PE = 1, or OE = 1
No
Error processing
Read FRBR
Read FLSR
DR = 0
Yes
All data read
Yes
Figure 15.5 Example of Data Reception Flowchart
[1]
Confirm that the DR flag in FLSR is 1 to ensure that
receive data is in the buffer. When the OUT2 bit in
FMCR and the ERBFI bit in FIER are set to 1, a
receive data ready interrupt occurs.
[2]
Read the RXFIFOERR, BI, FE, PE, and OE flags in
FLSR to ensure that no error has occurred. If an
[1]
error has occurred, perform error processing. When
the OUT2 bit in FMCR and the ELSI bit in FIER are
set to 1, a receive line status interrupt occurs.
[3]
Read the receive data in FRBR.
[4]
Check the DR flag in FLSR. When the DR flag is
[2]
cleared to 0 and all data has been read, data reception
is complete.
[3]
[4]
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