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10.5
Usage Notes
10.5.1
Conflict between FRC Write and Clear
If an internal counter clear signal is generated during the state after an FRC write cycle, the clear
signal takes priority and the write is not performed. Figure 10.8 shows the timing for this type of
conflict.
Write cycle of FRC
φ
Address
Internal write
signal
Counter clear
signal
FRC
Figure 10.8 Conflict between FRC Write and Clear
Section 10 16-Bit Free-Running Timer (FRT)
T 1
T 2
FRC address
N
Rev. 1.00 Mar. 12, 2008 Page 385 of 1178
H'0000
REJ09B0403-0100
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