Renesas H8S Family Hardware Manual page 831

(2) MII Register Access Procedure
The program accesses MII registers via the PHY interface register (PIR). Access is implemented
by a combination of 1-bit-unit data write, 1-bit-unit data read, bus release, and independent bus
release. Figures 20.8 to 20.11 show examples of MII register access timing. The timing will differ
depending on the type of PHY-LSI.
(1) Write to PHY interface register
MMD = 1
MDO = write data
MDC = 0
(2)
(3)
(1) Write to PHY interface register
MMD = 0
MDC = 0
(2) Write to PHY interface register
MMD = 0
MDC = 1
(3) Write to PHY interface register
MMD = 0
MDC = 0
Figure 20.9 Bus Release Flowchart (TA in Read in Figure 20.7)
Write to PHY interface register
MMD = 1
MDO = write data
MDC = 1
Write to PHY interface register
MMD = 1
MDO = write data
MDC = 0
Figure 20.8 1-Bit Data Write Flowchart
Section 20 Ethernet Controller (EtherC)
MDC
MDO
(1) (2) (3)
MDC
MDO
(1) (2) (3)
Rev. 1.00 Mar. 12, 2008 Page 783 of 1178
REJ09B0403-0100