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2
Section 18 I
C Bus Interface (IIC)
4. SCL and SDA input are sampled in synchronization with the internal clock. The AC timing
therefore depends on the system clock cycle t
Characteristics. Note that the I
system clock frequency of less than 5 MHz.
2
5. The I
C bus interface specification for the SCL rise time t
speed mode). In master mode, the I
one bit at a time during communication. If t
the time determined by the input clock of the I
extended. The SCL rise time is determined by the pull-up resistance and load capacitance of
the SCL line. To insure proper operation at the set transfer rate, adjust the pull-up resistance
and load capacitance so that the SCL rise time does not exceed the values given in table 18.12.
Table 18.12 Permissible SCL Rise Time (t
t
Indi-
cyc
TCSS IICXn
cation
0
0
7.5 t
cyc
1
17.5 t
cyc
1
0
1
1
37.5 t
cyc
Note: n = 0 to 5
Rev. 1.00 Mar. 12, 2008 Page 652 of 1178
REJ09B0403-0100
2
C bus interface AC timing specification will not be met with a
2
C bus interface monitors the SCL line and synchronizes
sr
2
I
C Bus Specification
(Max.)
Standard
1000
mode
High-speed
300
mode
Standard
1000
mode
High-speed
300
mode
Standard
1000
mode
High-speed
300
mode
, as shown in section 31, Electrical
cyc
is 1000 ns or less (300 ns for high-
sr
(the time for SCL to go from low to V
sr
2
C bus interface, the high period of SCL is
) Values
Time Indication [ns]
φ = 20 MHz
375
300
875
300
1000
300
) exceeds
IH
φ = 25 MHz
φ = 34 MHz
300
221
300
221
700
515
300
300
1000
1000
300
300
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