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Section 19 LPC Interface (LPC)
Bit
Bit Name Initial Value Slave Host Description
0
IRQ1E1
0
Rev. 1.00 Mar. 12, 2008 Page 702 of 1178
REJ09B0403-0100
R/W
R/W
Host IRQ1 Interrupt Enable 1
Enables or disables a host HIRQ1 interrupt request
when OBF1 is set by an ODR1 write.
0: HIRQ1 interrupt request by OBF1 and IRQ1E1 is
disabled
[Clearing conditions]
•
Writing 0 to IRQ1E1
•
LPC hardware reset, LPC software reset
•
Clearing OBF1 to 0
1: HIRQ1 interrupt request by setting OBF1 to 1 is
enabled
[Setting condition]
Writing 1 after reading IRQ1E1 = 0
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