Fifo Control Register (Ffcr) - Renesas H8S Family Hardware Manual

Section 15 Serial Communication Interface with FIFO (SCIF)
15.3.8

FIFO Control Register (FFCR)

FFCR is a write-only register that controls transmit/receive FIFOs.
Bit Bit Name
7 RCVRTRIG1
6 RCVRTRIG0

5, 4
3 DMAMODE
2 XMITFRST
1 RCVRFRST
0 FIFOE
Rev. 1.00 Mar. 12, 2008 Page 514 of 1178
REJ09B0403-0100
Initial Value R/W Description
0 W Receive FIFO Interrupt Trigger Level 1, 0
0 W These bits set the trigger level of the receive FIFO
interrupt.
00: 1 byte
01: 4 bytes
10: 8 bytes
11: 14 bytes
 
Reserved
These bits cannot be modified.

0 DMA Mode
This bit is not supported. The initial value should not
be changed.
0 W Transmit FIFO Reset
The transmit FIFO data is cleared when 1 is written.
However, FTSR data is not cleared. This bit is
automatically cleared.
0 W Receive FIFO Reset
The receive FIFO data is cleared when 1 is written.
However, FRSR data is not cleared.
This bit is automatically cleared.
0 W FIFO Enable
0: Transmit/receive FIFOs disabled
1: Transmit/receive FIFOs enabled
All bytes of these FIFOs are cleared.