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Figure 31.33 LPC Interface (LPC) Timing............................................................................... 1154
Figure 31.34 Timing of RM_REF-CLK and RMII Signals...................................................... 1155
Figure 31.35 RMII Transmit Timing........................................................................................ 1156
Figure 31.36 RMII Receive Timing (Normal Operation)......................................................... 1156
Figure 31.37 RMII Receive Timing (When an Error is Detected) ........................................... 1156
Figure 31.38 MDIO Input Timing ............................................................................................ 1157
Figure 31.39 MDIO Output Timing ......................................................................................... 1157
Figure 31.40 WOL Output Timing ........................................................................................... 1157
Figure 31.41 Data Signal Timing ............................................................................................. 1159
Figure 31.42 Load Condition.................................................................................................... 1159
Figure 31.43 JTAG ETCK Timing ........................................................................................... 1160
Figure 31.44 Reset Hold Timing .............................................................................................. 1161
Figure 31.45 JTAG Input/Output Timing................................................................................. 1161
Figure 31.46 Connecting Capacitors to VCC and VCL Pins.................................................... 1164
Appendix
Figure C.1 Package Dimensions (PLBGA0176GA-A) ............................................................ 1169
Figure C.2 Package Dimensions (PLQP0144KA-A)................................................................ 1170
Rev. 1.00 Mar. 12, 2008 Page xl of xIviii
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