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PCSR
Reso-
PWCKX0
lution
PWCKX1
T
C
B
A
CKS
(µs)
0
1
1
1
7.53
(φ/256)
1
0
0
1
30.12
(φ/1024)
1
0
1
1
120.47
(φ/4096)
1
1
0
1
481.88
(φ/16384)
1
1
1
1
Setting
prohibited
Note:
* Indicates the conversion cycle when specific DA3 to DA0 bits are fixed.
Conver-
Base
sion
TL/TH
CFS
Cycle
Cycle
(OS = 0/OS = 1)
481.9 µs
0
123.36 ms
Always low/high output
DA13 to 0 = H'0000 to H'00FF
2.1 kHz
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1927.5 µs 123.36 ms
1
Always low/high output
DA13 to 0 = H'0000 to H'003F
0.5 kHz
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
0
1.93 ms
493.45 ms
Always low/high output
DA13 to 0 = H'0000 to H'00FF
518.8 Hz
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
7.71 ms
493.45 ms
Always low/high output
DA13 to 0 = H'0000 to H'003F
129.7 Hz
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
0
7.71 ms
1.974 s
Always low/high output
DA13 to 0 = H'0000 to H'00FF
129.7 Hz
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
30.84 ms 1.974 s
Always low/high output
DA13 to 0 = H'0000 to H'003F
32.4 Hz
(Data value) × T
DA13 to 0 = H'0040 to H'3FFF
0
30.84 ms 7.895 s
Always low/high output
DA13 to 0 = H'0000 to H'00FF
32.4 Hz
(Data value) × T
DA13 to 0 = H'0100 to H'3FFF
1
123.36
7.895 s
Always low/high output
ms
DA13 to 0 = H'0000 to H'003F
(Data value) × T
8.1 Hz
DA13 to 0 = H'0040 to H'3FFF
Section 9 14-Bit PWM Timer (PWMX)
Fixed DADR Bits
Bit Data
Precision
(Bits)
14
12
10
0
0
14
12
10
0
0
14
12
10
0
0
14
12
10
0
0
14
12
10
0
0
14
12
10
0
0
14
12
10
0
0
14
12
10
0
0
Rev. 1.00 Mar. 12, 2008 Page 367 of 1178
Conversion
Cycle*
123.36 ms
0
0
30.84 ms
0
0
7.71 ms
123.36 ms
0
0
30.84 ms
0
0
7.71 ms
493.45 ms
0
0
123.36 ms
0
0
30.84 ms
493.45 ms
0
0
123.36 ms
0
0
30.84 ms
1.974 s
0
0
0.493 s
0
0
0.123 s
1.974 s
0
0
0.493 s
0
0
0.123 s
7.895 s
0
0
1.974 s
0
0
0.493 s
7.895 s
0
0
1.974 s
0
0
0.493 s
REJ09B0403-0100
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