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Section 22 USB Function Module (USB)
22.3.19 Data Status Register (DASTS)
DASTS indicates whether the transmit FIFO buffers contain valid data. A bit in this register is set
when data is written to the corresponding FIFO buffer and the packet enable bit is set. A bit in this
register is cleared when all data has been transmitted to the host, or when the FIFO clear bit for the
corresponding endpoint in the FIFO clear register (FCLR) is set.
Bit
Bit Name
7
6
5
EP3 DE
4
EP2 DE
3 to 1
0
EP0i DE
Rev. 1.00 Mar. 12, 2008 Page 848 of 1178
REJ09B0403-0100
Initial
Value
R/W
Description
0
R
Reserved
0
R
These bits are always read as 0. The initial value
should not be changed.
0
R
EP3 Data Present
This bit is set when the endpoint 3 FIFO buffer
contains valid data.
0
R
EP2 Data Present
This bit is set when the endpoint 2 FIFO buffer
contains valid data.
Reserved
All 0
R
These bits are always read as 0.
0
R
EP0i Data Present
This bit is set when the endpoint 0 FIFO buffer
contains valid data.
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