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SCL
(master output)
8
9
1
SDA
Bit 0
Bit 7
Bit 6 Bit 5 Bit 4 Bit 3 Bit 2
(master output)
Data (n-2)
[11]
SDA
(slave output)
A
IRIC
ICDRF
ICDRS
Data (n-2)
ICDRR
User processing
[13] IRIC clear
Figure 18.22 Slave Receive Mode Operation Timing Example (2)
2
3
4
5
6
7
8
Bit 1 Bit 0
Data (n-1)
Data (n-1)
Data (n-2)
[9] Wait for one frame
(MLS = ACKB = 0, HNDS = 0)
9
1
2
3
4
5
Bit 7 Bit 6 Bit 5 Bit 4 Bit 3 Bit 2 Bit 1 Bit 0
[11]
Data (n)
A
Data (n-1)
[13] IRIC clear
[10] ICDR read
[10] ICDR read
(Data (n-1))
(Data (n-2))
[9] Set ACKB = 1
Rev. 1.00 Mar. 12, 2008 Page 639 of 1178
2
Section 18 I
C Bus Interface (IIC)
Stop condition detection
6
7
8
9
[11]
[12]
A
Data (n)
Data (n)
[13] IRIC clear
[14] ICDR read
(Data (n))
REJ09B0403-0100
[15] IRIC clear
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